- #BROADWELL SMBUS CONTROLLER DRIVER HOW TO#
- #BROADWELL SMBUS CONTROLLER DRIVER DRIVERS#
- #BROADWELL SMBUS CONTROLLER DRIVER ARCHIVE#
- #BROADWELL SMBUS CONTROLLER DRIVER PATCH#
Why? Because we see on our system temperature sensors on i2c address i2c-1 0x18Īnd ic2-1 0x1a and BIOS and EDAC tell us we have DIMMs on channel 0:slot 0 and Smb_stat_0 and from Andy's dimm-bus.c driver, I gain the impression the mappingĬhannel 00 slot 00 i2c-1 0x18 (if there is a dimm)Ĭhannel 00 slot 01 i2c-1 0x19 (if there is a dimm)Ĭhannel 00 slot 02 i2c-1 0x1a (if there is a dimm)Ĭhannel 00 slot 03 i2c-1 0x1b (if there is a dimm)Ĭhannel 01 slot 00 i2c-1 0x1c (if there is a dimm)Ĭhannel 01 slot 01 i2c-1 0x1d (if there is a dimm)Ĭhannel 01 slot 02 i2c-1 0x1e (if there is a dimm)Ĭhannel 01 slot 03 i2c-1 0x1f (if there is a dimm)Ĭhannel 02 slot 00 i2c-2 0x18 (if there is a dimm)Ĭhannel 02 slot 01 i2c-2 0x19 (if there is a dimm)Ĭhannel 02 slot 02 i2c-2 0x1a (if there is a dimm)Ĭhannel 02 slot 03 i2c-2 0x1b (if there is a dimm)Ĭhannel 03 slot 00 i2c-2 0x1c (if there is a dimm)Ĭhannel 03 slot 01 i2c-2 0x1d (if there is a dimm)Ĭhannel 03 slot 02 i2c-2 0x1e (if there is a dimm)Ĭhannel 03 slot 03 i2c-2 0x1f (if there is a dimm)Įxperimentally, I gain the impression it's ratherĬhannel 01 slot 00 i2c-1 0x1a (if there is a dimm)Ĭhannel 01 slot 01 i2c-1 0x1b (if there is a dimm)Ĭhannel 03 slot 00 i2c-2 0x1a (if there is a dimm)Ĭhannel 03 slot 01 i2c-2 0x1b (if there is a dimm) The mapping of dimm to i2c adapter and addresses is confusing at best.
#BROADWELL SMBUS CONTROLLER DRIVER HOW TO#
I don't know how to do it better and even moveįor now the instantiations into the iMC SMBus driver itself
The iMC SMBus driver i2c-imc.c is calling dimm-bus.c to do its as already pointed out, the instantiations happen in a further driverĭimm-bus.c. The remaining 8 temperature sensors returned 0. Sensors, although our system had only 2 DIMMs (with 1 temperature sensorĮach). the probe function i2c_scan_dimm_bus() instantiates blindly 10 temperature I2c addresses of the actual temperature sensors are known to the memoryĬontroller (when in CLTT mode) and don't need to be blindly enumerated. That is dangerous (see comment in i2c-imc.c: if (stat & SMBSTAT_SBE)). Sensor i2c addresses causing the SBE bit to be set 6 times on our system. the probe function i2c_scan_dimm_bus() blindly enumerates potential DIMM The original patch-set also provided an additional driver, dimm-bus.c, to
#BROADWELL SMBUS CONTROLLER DRIVER PATCH#
Our patch provides proper arbitration between OS and firmware on Broadwell. set tsod_polling_interval to the previous value OS has now exclusive access to the smb bus wait 10 ms to drain a potential in-flight firmware CLTT transaction don't (necessarily) disable CLTT mode, but set tsod_polling_interval to 0
#BROADWELL SMBUS CONTROLLER DRIVER DRIVERS#
Specification (EDS), Volume Two: Core and Uncore Registers Volume 2 of 5 Rev.Ģ.3) hints how to make OS drivers and firmware co-exist in CLTT mode. Our documentation (Intel Xeon Processor D-1500 Product Family External Design Time, support for more memory controllers should be added. We rewrote this driver to support Broadwell's memory controller 8086.6fa8. We ran this driver on our Broadwell CPU and theĭriver's internal consistency check failed every 30 min or so. Was in CLTT mode as the driver and firmware were both accessing the memoryĬontroller without arbitration. It was not possible to use this driver while the memory controller Either the Sandy Bridge documentation is incomplete or the functionality The original driver was written for the memory controller found in Sandy BridgeĬPUs. Patch-set, instantiated the thermal sensors. A second driver dimm-bus.c, also part of Andy's The original driver i2c-imc.c was an iMC SMBus controller that provided access Only one mode of operation can be used at a time. Sensor over the SMBus but approximates/guesses its temperature.ĭepending on the temperature, the memory controller firmware may throttle the OLTT: The memory controller firmware is not accessing the DIMM temperature CLTT: The memory controller firmware is periodically accessing the DIMM Of operation: Closed Loop Thermal Throttling (CLTT), Open Loop Thermal The memory controller firmware has three modes Modern Intel memory controllers host an SMBus controller and connection toĭIMMs and their thermal sensors. This patch is based on Andy Lutomirski's iMC SMBus driver patch-set To: linux-i2c, linux-kernel, Andy Lutomirski +Cc: Stefan Schaeckeler ` (2 more replies) 0 siblings, 3 replies 8+ messages in threadįrom: Stefan Schaeckeler 22:51 UTC ( / raw)
#BROADWELL SMBUS CONTROLLER DRIVER ARCHIVE#
LKML Archive on help / color / mirror / Atom feed * i2c: imc: Add support for Intel iMC SMBus host controller. I2c: imc: Add support for Intel iMC SMBus host controller.
0 kommentar(er)
